How Much Power Cmos Camera Requires
Sensors (Basel). 2020 Jul; 20(xiii): 3649.
Design of an Edge-Detection CMOS Paradigm Sensor with Built-in Mask Circuits
Received 2020 May 12; Accepted 2020 Jun 28.
Abstract
In this paper, nosotros propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal eight-bit images for low-power estimator vision applications. To find the edges of images in the CIS, neighboring column data are compared in in-column memories after cavalcade-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex prototype indicate processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A paradigm sensor with 1920 × 1440 resolution was made with a ninety-nm 1-poly 5-metal CIS process. The surface area of the iv-shared 4T-active pixel sensor was one.4 × 1.4 µmtwo, and the scrap size was 5.xv × 5.xv mm2. The full power consumption was 9.4 mW at 60 fps with supply voltages of iii.3 Five (analog), 2.8 5 (pixel), and i.2 5 (digital).
Keywords: CMOS image sensor, computer vision, border detection, depression power consumption, single-slope ADC
1. Introduction
In recent years, complementary metallic-oxide-semiconductor (CMOS) epitome sensors (CIS) with computing functions (called computer vision sensors) have received considerable attention for use in a wide diversity of applications, such as medical imaging, automotive safety, surveillance, and face detection for auto-focus in digital cameras [i,two,3,four,5,vi,7]. For edge/face up/object detection processing in mobile applications that are battery powered, low power consumption is a primary pattern benchmark. In essence, estimator vision (CV) sensors capture, procedure, analyze, and understand the objects [8,nine,x,11]. To notice objects using CV computation, two types of approaches have been developed: (1) asynchronous and event-based sensors, such as dynamic vision sensors (DVS), and (ii) frame-based CIS with CV ciphering hardware.
Result-based sensors, such as DVS [12], asynchronous time-based epitome sensors [10], and dynamic and agile-pixel vision sensors (DAVIS) [eleven], have been developed for depression-latency CV computation. DVS asynchronously detects pixel-level temporal differences in images, called an "event" within a microsecond of time, and transmits the output to track fast-moving objects [13,fourteen]. Furthermore, since no information is transformed without events, power consumption at the system level can be saved and reduced past a factor of 100 compared with the frame-based CIS with CV hardware. Nevertheless, DVS only informs 1-bit resolution output that has an ten, y-accost in the pixel array in which temporal contrast changes. Hence, the outputs of DVS cannot be adapted for traditional CV algorithms that require static scene information rather than dynamic event information. Every bit another blazon of event-based sensor, DAVIS combines the advantages of the ii types of sensors: DVS and frame-based CIS. Withal, while DVS tracks the dynamic events of temporal difference, frame-based CIS captures static scene information to apply traditional CV algorithms with additional CV hardware, leading to high power consumption and high latency. In addition, a pixel of asynchronous sensors consists of a photodiode, 47 transistors, and 2 capacitors, while traditional active pixel sensors (APS) take 4 transistors (four-T) and a photodiode only. Therefore, the fill factor (ratio of pixel array'south light-sensitive area to its total expanse) of DVS is about twenty~thirty%, then at that place is a limitation in achieving high image resolution sensors (~magnitude of megapixels).
On the other manus, framed-based CIS has been used with CV computation hardware in a range of applications [8,9]. In frame-based CIS, the analog information in voltage acquired from conventional 4-T APS is converted to the digital domain using an analog-to-digital converter (ADC). The digitized outputs are sent to an paradigm signal processor (Isp) that performs sure CV operations to analyze and understand the information received from the private pixels to detect features such as faces, pedestrians, and gestures. Owing to the mature development of APS and ADC, loftier-operation and high-resolution frame-based CIS tin can be used for further CV applications, such as long-distance object detection for surveillance sensing systems. However, reading out the image information frame past frame causes frame-based CIS to suffer from a long data-processing time as image resolution increases [15,16]. In addition, since CV processing to detect face or other objects requires significant ability consumption, this approach cannot be readily practical to mobile applications considering of its lower battery life.
Therefore, for power-efficient CV operations, by taking reward of mature APS and ADC, elementary CV ciphering hardware for edge detection can be implemented in column-parallel peripheral circuitry based on a frame-based CIS structure. In this paper, we propose a power-efficient CIS with a built-in mask that outputs edge images without an additional ISP past using the conventional CIS construction. In add-on, the proposed CIS can selectively capture either edge-detection images or normal 8-scrap images that enable static scene information to be used for existing CV algorithms. The contents of this paper are every bit follows. Section two discusses the proposed edge-detection CIS alongside its circuit design and implementation. The experimental results and conclusions are summarized in Department iii and Section 4, respectively.
two. Design of the Proposed Edge-Detection CMOS Image Sensor
2.one. Existing Edge-Detection Mask Algorithm
To detect edges, the mask-processing technique is generally used. Using the mask, the edges are recognized equally a valid value, and the rest of the image data are zeroed. Because the edges are always constant regardless of the illuminance, edge images are independent of the measurement environment. Effigy 1a shows the principle of the mask-processing technique for edge detection. When a iii × 3 mask is overlaid on the original target image, each cell of the mask is practical to eight pixels effectually the center pixel (x, y). The cells A–I of the mask each give a constant weight to the coordinates of the image pixel. The center pixel (x, y) is multiplied past the weight of each mask cell and the pixel value then added together to change to a new M (10, y). This procedure is applied to all cells that correspond to the epitome resolution to form a new epitome. In dissimilar types of mask techniques, such every bit Sobel, Canny, Prewitt, Roberts, Laplacian, and Gaussian, edges can be obtained with different weights [17,xviii]. As shown in Effigy 1b, there are different types of edges: a ramp edge and a line edge. The ramp edge changes the brightness of the pixel subsequently it rapidly changes brightness. On the other hand, the line edge changes instantaneously then returns to the initial value. In reality, virtually of the edges are in the form of ramp edges, and so converting them to line edges is the principle of edge detection [17]. As can be seen from the waveforms of the two edges in Figure ib, the change from the ramp edge to the line edge is equivalent to differentiating the ramp edge waveform. That is, by detecting when there is a sudden alter in paradigm pixel data, an border of the prototype tin be detected. The basic shapes of different types of masks, such equally Sobel, Canny, Prewitt, and Roberts, are the aforementioned. The larger the data change from the center pixel to the nearby pixel, the more than the Thousand (x, y) value is increased. When the calculated value exceeds a specific threshold, Chiliad (x, y) is defined as edge information, resulting in 'ane'. On the other paw, if One thousand (x, y) is less than the threshold, it is defined every bit '0'. Since these techniques notice horizontal and vertical edges separately, ii masks for horizontal and vertical edges are required. Afterward processing horizontal and vertical edges, the consequence of the two masks is added through OR logic. However, such existing mask techniques simultaneously require three columns and three rows for 1 mask process. To implement these existing mask techniques, border-detection mask processing is performed in an additional chip called an ISP, which communicates with a conventional CIS flake. In add-on, conventional CISs read out the pixel information row by row, and a row buffer to shop the pixel information of these 3 rows is required, increasing the overall expanse and power consumption [7]. In this instance, the boosted row buffer increases power consumption and requires high-speed operation because of the additional operation of the row buffer consisting of additional memory blocks.
(a) Principle of the mask technique and (b) different types of edges.
To implement the border-detection process in a conventional CIS, a row buffer with several rows has been used to design a 3 × 3 mask circuit in a circuit, which greatly increased the layout size and power consumption of the entire cake [5]. Additionally, a global shutter method through an in-pixel ADC has been used [6], which requires a unlike type of pixel pattern. This in-pixel ADC decreases the pixel's fill up factor, thus greatly increasing the unit jail cell size of the pixel. In plow, this limitation prevents high resolution from being achieved. Some other arroyo can detect fixed pixel values of edges for iris recognition without using a mask algorithm [seven]. Nonetheless, the data value of the iris is assumed to range from 120 to 180 on the basis of eight-bit 256 codes, so obtaining edge images can vary depending on the illuminance. To create a power-efficient edge-detection CIS, we propose a new mask technique that can be implemented in a CIS'due south column-parallel ADC without a row buffer while minimalizing the conventional CIS construction. In addition, the proposed mask excursion enables the CIS to obtain border images regardless of the illuminance with low power consumption.
2.2. Proposed Algorithm for Edge Detection
The proposed edge-detection algorithm uses the read-out procedure of the proposed CIS, in which all cavalcade data are sequentially read as 8-scrap signals. The read-out performance of a conventional CIS is every bit follows. First, when the pixels of one row are selected, all the cavalcade data of the row are stored in static random-access retentiveness (SRAM) past each column ADC so read out sequentially from the first column. In this process, the deviation in the output code of information between next columns that are stored in SRAM tin can be obtained to detect edges. Figure 2 shows an example of edge detection during the read-out process. When the threshold value of the lawmaking deviation between two columns that are judged as an edge is x, 110 lawmaking changes are present from 001,011,002 (C1) to 100,110,10two (C2), resulting in an border. On the other mitt, if i code change exists from 100,110,10ii (C3) to 001,011,002 (C4), the region is not an edge because one is less than the threshold of 10. The proposed algorithm can perform functions such as a vertical edge-detection mask because the data-output code difference between columns is detected every bit an edge. Figure iii shows a comparison of the edge images and mask for a Laplacian mask and the proposed mask. The edge-detection algorithm recognizes only the border of the unabridged image as a valid value and sets all the remaining data to zero. In detail, the road has a diagonal shape, so the shape of the road is accurately recognized even by edge detection between vertical directions. In add-on, past detecting only 1 vertical edge, the effect shows that the proposed mask is less sensitive to noise compared with the Laplacian mask. Additionally, the proposed mask can be easily implemented in the conventional CIS structure because of the mask's simplicity, and the proposed edge-detection CIS can selectively capture either border-detection 1-bit images or normal 8-bit images.
Edge-detection process during readouts in CMOS image sensors (CISs).
Comparing of the Laplacian and proposed masks: (a) an original image and an edge image that uses (b) a Laplacian mask (for eight neighboring pixels) and (c) the proposed mask.
2.three. Operation Principle of the Edge-Detection CMOS Image Sensor
Figure 4 shows a block diagram of the proposed edge-detection CIS when using an 8-bit single-slope ADC (SS-ADC). The SS-ADC has been generally used in CIS because of the small-scale area and uncomplicated structure [19,20,21,22,23,24,25,26]. The resolution of the CIS is 1920 × 1440 with a 4-shared APS array. Unlike conventional CISs, an border detector is implemented past using a flip-bomb and an sectional-OR (XOR) gate. An input bespeak that is received by a pixel is candy by one row through a rolling-shutter method, and a digitally coded multi-bit indicate is stored in each column's 8-bit SRAM array. When processing one row, 8-fleck signals of each cavalcade in the 8-bit SRAM are output as a serial of digital pulse signals, D_out<due north>, as shown in Figure v.
Block diagram of the proposed edge-detection CIS.
(a) Timing diagram and (b) circuit of the border detector.
The edge-detector circuit can detect the positive and negative edges of D_out<n> and tin can find the change in each bit output from the SRAM. The bit of the edge detector is determined according to the edge threshold. The difference between adjacent pixels that exceed the xv least meaning $.25 (LSB) out of 256 full-calibration codes is less than x% of the entire prototype, and this value decreases as the image resolution increases [27]. Therefore, if the deviation is more 8 LSB in the image, the alter could be considered sufficiently sudden, and the region could be candy every bit an edge in the image. Therefore, the v nearly pregnant bits (MSB) of the 8-bit SRAM output go to 5-bit signal edge detectors because the edge threshold is 8 LSB by default. The edge threshold is selectable among viii, 16, and 32. Yet, in some cases, the value of the most significant six bits may be changed by a carry that is caused by a lower fleck, for example, from 000,001,11two to 00001000ii. To avert this instance, nosotros designed an fault-correction logic consisting of multiplexers (MUX) by calculation an offset to the n + one column. For example, when the MSB of 3-fleck SRAM (not used for edge detection) is 'H', the carry generation indicate controls a mux to select the Qb instead of Q, leading to a '−1' code commencement of the LSB of 5-scrap static random admission memory (SRAM) [28].
3. Experimental Results
3.i. Simulation Results and a Chip Photograph
The proposed edge-detection CIS was designed and fabricated with a xc-nm 1-poly v-metal CIS backside illumination process. The supply voltages are iii.3, 2.viii, and 1.two V for analog, pixel, and digital excursion blocks, respectively. The image resolution is 1920 × 1440 pixels, and the ADC resolution is 8 bits for normal images. Figure 6 shows the timing diagram of the 8-bit SS-ADC. The input voltage range of ADC is from 1.5 to 2.2 V. With the pixel voltage (5IN), ramping voltage (5RAMP) is entered to two inputs of a comparator. When the FiveRAMP is equal to VIN, the output of the comparator is flipped from logic 'L' to 'H'. An viii-scrap digital counter starts counting the time that the comparator is flipped from the starting VRAMP. For example, when VIN is 2.ii V (the maximum voltage of the ADC input range), the darkest images are obtained, resulting in 0 code. On the other mitt, when VIN is 1.five V, the brightest images are obtained, resulting in the total code of output, 256 codes. It should be noted that the 1 LSB of the ADC in fourth dimension is 0.98 ns in this paper. Table ane shows the post-layout simulation results in the process, supply voltage, and temperature variations. The best case is FF corner, 3.63 V analog supply voltage (AVDD), and −45 °C temperature, while the worst instance is SS corner, 2.97 Five AVDD, and 135 °C temperature. The post-layout simulation results indicate that the standard divergence of ane LSB is less than 0.018 LSB in the procedure, supply voltage, and temperature variations.
Cursory timing diagram of the CIS functioning.
Table i
ΔLSB (=0.985 ns) of an viii-bit ADC under process variation (unit: ns).
| Corner | Max. | Min. | Mean | Std. Dev |
|---|---|---|---|---|
| Best | ane.010 | 0.969 | 0.980 | 6.16 × x−3 |
| Nominal | ane.010 | 0.970 | 0.981 | five.17 × 10−3 |
| Worst | 1.250 | 0.924 | 0.983 | 1.80 × 10−2 |
The layout and a photograph of the proposed CIS are shown in Figure 7a,b, respectively. The cavalcade-parallel ADC circuits are located on the acme and bottom of the pixel array to secure the layout area of the cavalcade-parallel ADC circuits. The pitch of a pixel is 1.four μm, and the pitch of column-parallel ADC is two.eight μm. The core size, excluding the I/O pad, is 3.75 mm × 3.75 mm, and the APS array size is ii.68 mm × 2.02 mm. The fill cistron is approximately 52.55%, and the total power consumption at 60 fps is nine.4 mW.
(a) Chip layout of the proposed CIS and (b) microphotograph of the fabricated CIS.
3.2. Measurement Results
The full flake was measured by using a field-programmable gate assortment (FPGA) board to produce the required control signals for the operation of the clocked comparator, memory block, and so on. A point that was configured through Xilinx was applied to the pattern circuit through the motherboard by using the FPGA board, and the data were received and measured by the computer. The proposed CIS tin can capture both normal 8-bit images and edge images, examples of which are shown in Figure eight.
(a) An 8-chip black and white paradigm and (b) an edge epitome with the proposed mask circuits.
Tabular array 2 shows the comparison results of Pratt's effigy of merit (PFOM) with other masks, such as Sobel, Roberts, and Prewitt. PFOM [29] is given as
where IN = max{IA , II }, and IA and II are the number of pixels of a reference image and test paradigm, respectively. Since nosotros compared the same image resolution for the reference image and examination images, IA is equal to II , which is 2,764,800 (1920 × 1440). d is the distance of separation of an bodily edge pixel to a line of reference edge pixel, and a is the scaling abiding (=1/ix post-obit Pratt'southward original work). We chose an edge epitome with the Sobel mask as a reference image and evaluated PFOM. Since a examination border image with the Sobel mask is the same equally the reference paradigm with the Sobel mask, PFOM is 100%, while dissimilar masks show degradation of PFOM. In the edge image captured past the proposed CIS in edge detection mode (output is i-bit), PFOM is the lowest (PFOM: 94.96). However, we observed that with a change in the border threshold from xvi LSB to eight LSB, the PFOM increased to 95.50%. Since the proposed border detection excursion is capable of column-wise detection only, the mask is far simpler than others. Even so, PFOM can be improved with configurable edge thresholds.
Table 2
Comparison of PFOM of other masks with an image captured by the proposed CIS (8-chip, Figure eighta) and this work with an border detection sensor (1-chip, Figure 8b).
| PFOM (%) | Sobel | Roberts | Prewitt | This Work |
|---|---|---|---|---|
| Sobel (reference) | 100 | 96.50 | 99.75 | 94.96 |
In addition, we compared the PFOM and edge images of the Sobel mask and the proposed mask with different lux, as shown in Effigy 9. We chose the edge image with 700 lux of illuminance as a reference image and calculated PFOM. With dissimilar lux, some parts of the exam images are saturated in 1800 lux or non distinguishable in 700 lux. Although the proposed mask is capable of column-wise detection but, the degradation trend of PFOM with dissimilar illuminances is similar to that of the Sobel mask, which has both column- and row-wise border detection.
Comparison of edge images between Sobel and the proposed mask with different illuminances.
Figure 10 shows the noise performance of the proposed CIS. It should exist noted that the ADC of the input range is about 700 mV, and 1 LSB is 2.73 mV. The noises were measured under dark illuminance with 8× of analog gain. When operating equally an 8-bit paradigm sensor, pixel stock-still pattern noise (PFPN) is within 4 LSB (i.367 mV), and column fixed design racket (CFPN), row fixed pattern noise (RFPN), and random noise (RN) were both measured within one LSB (342 μV).
Dissonance measurement results of the proposed CIS (viii-flake images) with different illuminances.
Tabular array 3 summarizes the main functioning indicators of the proposed edge-detection image sensor. Table 4 compares this sensor's performance with those of other existing edge-detection image sensor circuits. In [5], a digital circuit that implements the commonly used mask technique is reported. After scanning multiple rows simultaneously and computing horizontal, vertical, and diagonal edges, the area of the digital circuit was quite big, resulting in low resolution, low conversion speed, and high ability consumption. In [six], the analog signal was direct converted to the frequency domain signal at the same time that the mask technique was applied to reduce power consumption and achieve high-speed conversion. Thus, the resolution was quite depression, prohibiting its use for high-resolution CIS applications.
Table 3
Performance summary of the proposed edge-detection CIS.
| Array Format | FHD (1920 × 1440) |
|---|---|
| Pixel Size | ane.iv µm × 1.iv µm |
| ADC Resolution | 8-bit |
| Frame Rate | threescore fps |
| Dynamic Range | 61 dB |
| Power Supply | three.iii V (analog)/2.8 V (pixel)/1.ii V (digital) |
| Power Consumption | 9.4 mW |
| 90 µW (per cavalcade) | |
| 0.4 µW (per column at power shutoff) | |
| Expanse | 26.57 mm2 (v.15 mm × five.xv mm) |
| Process | 90-nm 1P5M BSI CIS |
Table iv
Performance comparison of the proposed CIS.
In [7], the circuit size was reduced by using the histogram distribution of the paradigm without the mask, but unstable border images under different illuminations were obtained. In this paper, we advise a built-in mask in CIS without increasing the area compared with that of conventional CISs. In add-on, a stable and high-resolution border image can be obtained regardless of the illumination. Different other mask algorithms, the proposed mask algorithm can exist practical to any type of column-parallel ADC. Therefore, speed and ability consumption can be farther improved by using various ADCs.
4. Conclusions
In this paper, we nowadays an edge-detection CIS with a proposed congenital-in mask that was fabricated in a ane-poly v-metal 90-nm CIS process. We show that the congenital-in masks for a simple CV office like border detection can exist implemented in cavalcade-parallel circuits without an additional ISP. The proposed mask excursion, consisting of an additional XOR and a flip-flop in each column, performs edge detection while maintaining the column-parallel SS-ADC in the conventional CIS structure. We demonstrate that both normal viii-scrap images and edge-detection images can be obtained with 9.four mW of power consumption at sixty fps. Therefore, the proposed built-in mask can apply any cavalcade-parallel ADC types, such every bit successive approximation registers, sigma-delta, etc., to add edge-detection functions. Nosotros believe that the proposed border-detection CIS tin can be used for low-ability computer vision applications in a variety of consumer electronics that have limited ability budgets.
Acknowledgments
The EDA tool was supported by the IC Pattern Education Heart (IDEC), Korea.
Writer Contributions
M.J. and Thousand.S. conceived and designed the circuits. H.N. and S.Y.M. performed the experiments and analyzed the data. All authors were involved in the preparation of this manuscript. All authors have read and agreed to the published version of the manuscript.
Funding
This work was supported in part by the MSIT(Ministry of Science and ICT), Korea, nether the ITRC(It Research Middle) support programme(IITP-2020-2018-0-01421) supervised by the IITP(Establish for Information & Communications Applied science Planning & Evaluation) and in part by the National Research Foundation of Korea (NRF) grant funded by the Korea regime (MSIT) (No. 2020R1A2C1009583).
Conflicts of Involvement
The authors declare no disharmonize of interest.
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Source: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC7374416/
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